1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and, more particularly, it relates to an improvement on a heavily loaded signal line that is adapted to operate at a high frequency.
2. Description of the Related Art
In recent years, under the circumstances where microprocessors are designed to operate at high speed, there is a strong demand for dynamic random access memory (DRAM) devices operating as main memories that offer a high access speed exceeding 100 MHz. In an attempt to meet the demand, a number of synchronous semiconductor memory devices have been developed (see: JP-A-61-148692, JP-A-6-76566 & JP-A-8-96573). A synchronous semiconductor memory device latches an external address with a data write/read instruction and executes the operation of reading/writing the data at the external address and then it receives a synchronous clock signal and generates predetermined internal addresses starting from the external address to read/write the data at the internal addresses. Thus, a synchronous DRAM is a DRAM that operates in synchronization with a clock signal, so that the data with the addresses that are internally and automatically generated following the data at the address latched by a read/write instruction are continuously output at high speed or data are input to the addresses continuously at high speed. This is called a burst operation.
In a prior art synchronous semiconductor memory device including a memory cell array, a burst counter for generating an internal address signal in synchronization with an external clock signal and a decoder for reading out data from the memory cell array according to the internal address signal, an internal clock generation circuit generates an internal clock signal having a frequency equal to the frequency of the external clock signal, and a data output circuit outputs the data read out of the memory cell array in synchronization with the internal clock signal. This will be explained later in detail.
In the above-described prior art synchronous DRAM device, however, the internal clock signal operates at the same frequency as that of the external clock signal, so that the life span of a signal line for the internal clock signal is reduced by deterioration of its reliability due to electro-migration.